1. Field of the Invention
The invention herein relates to microprobes for testing of integrated circuits, and more particularly, to a compliant membrane probe.
2. Description of the Related Art
Current thin film interposer (TFI) technology has provided significant performance improvements over existing vertical probe technologies. Reference may be had to existing thin film interposer technology from International Business Machines, Inc. of Armonk, N.Y. However, TFI is mechanically limited due to involvement of a rigid probe. For example, rigid probes may not conform well to non-planar samples that arise in a test environment. Examples include non-planar situations arise in “controlled collapsible chip connections” (C4). Commonly used controlled collapsible chip connections often include solder balls having a solder of about 97% lead and 3% tin. Diameters of the balls typically range from about 75 to about 125 micrometers, and provide for a chip-to-carrier interconnect.
The C4 process includes arranging an array of these balls or bumps on the surface of a chip, either in an area array or peripheral configuration. The chip is placed face down on a carrier. When heat is applied, the solder reflows to the pads joining the chip to the carrier. A non-planar C4 array profile can result from uneven thermal response during the reflow process, as well as temperature gradients within the chip during test.
Various testing apparatus include design features to compensate for an uneven profile. For example, rigid probes compensate for the initial non-planar relationship of controlled collapsible chip connections by mechanically deforming all of the connections until contact is made with each one. This requires a significant amount of force and is reaching the limits of current test hardware (Prober, probe cards, product wafer). Further, this may be detrimental to at least one of the chip and the connections.
What are needed are techniques for making reliable test connections with a plurality of controlled collapsible chip connections. Preferably, the techniques minimize the deformation of the chip connections and do not require an application of excessive force. What are needed are techniques such as those disclosed herein.